1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a dynamic random access memory (DRAM) provided with an additional memory cell block having an irregular memory cell arrangement to hold parity bits.
2. Description of the Background Art
Conventionally, a semiconductor memory device such as a DRAM is configured such that, when a defective memory cell occurs, a column including the defective memory cell is detected and then the defective memory cell is remedied by substituting a spare redundant column provided separately for the column including the defective memory cell.
FIG. 4 is a schematic block diagram showing an example of a DRAM provided with such redundant column. Referring to FIG. 4, row address and column address signals A.sub.0, A.sub.1, ..., A.sub.7, A.sub.8 are applied from an external address signal source (not shown) to a row address and column address buffer 2 on a chip 1, while a row address strobe signal (RAS), a column address strobe signal (CAS), a write enable signal (WE) and an Output enable signal (OE) are applied as various control signals from an external control signal source (not shown) to a control clock generating circuit 3 on chip 1.
A memory cell array divided into eight blocks 4-11 is provided on chip 1. Any of word lines WL0-WL512 passing through foursmemory cell blocks 4-7 on the left side of FIG. 4 is selected by a row decoder 12 based on a row address signal from aforementioned address buffer 2 and any of word lines WL0-WL512 passing through four memory cell blocks 8-11 on the right side is selected by a row decoder 13 based on the row address signal from address buffer 2.
Meanwhile, any of column selection lines CSL0-CSL127 passing through two uppermost memory cell blocks 4 and 8 in FIG. 4 is selected by a column decoder 14 based on a column address signal from the aforementioned address buffer 2, any of column selection lines CSL0-CSL127 passing through two memory cell blocks 5 and 9 in the second stage is selected by a column decoder 15 based on the column address signal from address buffer 2, any of column selection lines CSL0-CSL127 passing through two memory cell blocks 6 and 10 in the third stage is selected by a column decoder 16 based on the column address signal from address buffer 2, and any of column selection lines CSL0-CSL127 passing through two lowermost memory cell blocks 7 and 11 is selected by a column decoder 17 based on the column address signal from address buffer 2. The operation timing of aforementioned row decoders 12, 13 and column decoder 14-17 is controlled by clock signals generated from control clock generating circuit 3.
Data is written into and read out from a memory cell thus selected by a row address signal and a column address signal via an I/O switch 18 or 19, which will be described later. In the middle of each memory cell block a sense amplifier SA is provided to amplify the data read out from each memory cell.
Exchange of write/read data with the outside of the chip is carried out in parallel on a 8-bit basis through an input/output terminal 20 and an input/output buffer 21. The data transfer timing between the input/output buffer 1 and aforementioned I/O switches 18 and 19 and the data transfer timing between the input/output buffer 21 and input/output terminal 20 are controlled by clock signals generated from control clock generating circuit 3.
Here, in the DRAM of FIG. 4, memory cell blocks 22a and 22b for redundant columns are provided in addition to the aforementioned eight memory cell blocks. Any of word lines WL0-WL512 passing through the redundant memory cell block 22a on the left side is selected by row decoder 12 based on the row address signal, and any of word lines WL0-WL512 passing through the redundant memory cell block 22b on the right side is selected by row decoder 13 based on the row address signal. Either column selection line CSL0 or CSL1 passing through the redundant memory cell blocks 22a and 22b is selected by a redundant column decoder 23 based on the column address signal. The operations of redundant memory cell blocks 22a and 22b and redundant column decoder 23 will be described later in detail.
FIG. 5 is a circuit diagram showing a main portion of a DRAM in FIG. 4 in detail. FIG. 5 shows a main portion of two bit line pairs connected to a certain column selection line CSL extended from column decoder 17 among a plurality of bit line pairs which configure memory cell block 11 in FIG. 4 and elements associated therewith as well as a main portion of two bit line pairs connected to a certain column selection line CSL1 extended from redundant column decoder 23 among four bit line pairs which configure redundant memory cell block 22b in FIG. 4 and elements associated therewith. As shown in FIG. 5, two bit line pairs are connected to one column selection line CSL in a normal memory cell block 11, and also two bit line pairs are connected to one redundant column selection line CSL in redundant memory cell block 22b in the same manner.
In memory cell block 11, on writing and reading data, one column selection line CSL is selected by the corresponding column decoder, I/O gate transistors 30 of two bit line pairs connected to the column selection line are turned on and the two bit line pairs are connected to I/O lines 31. I/O lines 31 are connected to input/output buffer 21 (FIG. 4) through an I/O switch 19. Since the operation of writing and reading data in normal memory cell block is well known, more detail description will be omitted.
The operation of redundant memory cell block 22b and redundant column decoder 23 will be described. These memory cells for redundant column are provided, in case of occurrence of defect in a memory cell included in a normal memory cell block, to remedy the defective column including the defective memory cell. More specifically, each decoder is programmed such that when any defective memory cell has been detected in a normal memory cell block and its column address is designated by an external input, redundant column decoder 23 activates either one of two redundant column selection lines CSL0 and CSL1 in response, and replaces bit line pairs which correspond to the aforementioned defective column by two bit line pairs connected to the activated line. In redundant memory cell block 22b, I/O gate transistors 40 of two bit line pairs connected to the activated redundant column selection line CSL is turned on, and two bit line pairs are connected to I/O lines 41.
An I/O switch 19 is provided between I/O lines 31 and 41 from normal memory cell block 11 and from redundant memory cell block 22b and input/output buffer 21 (FIG. 4). When the redundant column decoder activates any of CSL lines to use a redundant column, this I/O switch 19 functions so that it selects I/O lines 41 according to a signal from redundant column decoder 23 and connects those lines to input/output buffer 21. Thus, the defective memory cell in the normal memory cell block is replaced by a redundant memory cell.
In the aforementioned example shown in FIG. 4, all the normal memory cell blocks as well as all the column decoders have the same structure (same column decoder address) one another, and therefore one type of the redundant column (i.e. redundant memory cell blocks 22a and 22b and redundant column decoder 23) could cope with (remedy) the defective memory cell occurred in any memory cell block.
Meanwhile, generally in a DRAM, (for example 8-bit) data read/written sometimes accompanies a known (for example 1-bit) parity bit for error correction. When accompanies the parity bit, further memory cell block for parity bits must be added to the memory cell array arrangement in FIG. 4. FIG. 6 is a diagram schematically showing a configuration of a DRAM having an additional memory cell block for parity bits like this and an additional column decoder therefor.
In FIG. 6, DRAM memory cell array arrangement has an additional memory cell block 35 for the parity bits and additional column decoder 36 in addition to the configuration of FIG. 4, and additional memory cell block 35 has a rectangular structure (memory cell arrangement) which is different from each of normal memory cell blocks 4-11 from the viewpoint of layout of the entire memory cell array.
Since all of aforementioned normal memory cell blocks 4-11 have the same configuration (memory cell arrangement) and therefore share the same column decoder address, one type of a redundant column (redundant memory cell blocks 22a and 22b and redundant column decoder 23) could cope with the occurrence of defective memory cell in any memory cell block, but when memory cell block 35 which has a different configuration as shown in FIG. 6 is added, conventional one type of redundant column cannot cope with (remedy) the defective column in the additional memory cell block 35.
Here, it is necessary for each type of memory cell blocks to provide its own redundant column for the memory cell array including two types of memory cell blocks as shown in FIG. 6 to remedy the defective memory cell array, but in such case the area of chip 1 itself increases.